Announcing Drone 0.14

The main focus of this release was adding experimental support for the new RISC-V hardware architecture. We had two dev boards to experiment with: SiFive HiFive1 Rev B and Sipeed Longan Nano. Both were running on RV32IMAC variant RISC-V cores. The “A” letter means that the core implements the Atomic Instructions Standard Extension. And while the HiFive1’s core implements this extension on paper, it has a critical limitation - LR/SC instructions, which are used to implement the atomic CAS (compare-and-swap) operation, are not supported in the RAM region. Making it not compatible with Drone requirements for hardware atomics. However the Longan Nano’s core implements the Atomic Extension correctly and without limitations, hence it becomes the first RISC-V board that runs Drone OS, and here is the blinking demo application: longan-blink.

RISC-V specification describes a very basic interrupt controller named CLINT. It lacks crucial features that other controllers like Cortex-M’s NVIC have, namely prioritization and pre-emption. We decided to implement the missing pieces in software. Hence we introduce a new drone_core::thr::soft! macro and drone_core::thr::soft module. The basic drone_core::thr! becomes drone_core::thr::pool!, Cortex-M’s drone_cortexm::thr! becomes drone_cortexm::thr::nvic!, and RISC-V’s variant is drone_riscv::clint!.

Other important changes include:

There are other changes in the Drone 0.14 release: check out what changed in drone, drone-core, drone-cortexm, and drone-stm32-map.